
module riscv_imm_gen(
    input [2:0] ext_op,
    input [31:0] inst_val,
    output reg [31:0] imm_out
);

wire [31:0] immI;
wire [31:0] immU;
wire [31:0] immS;
wire [31:0] immB;
wire [31:0] immJ;

assign immI = {{20{inst_val[31]}}, inst_val[31:20]};
assign immU = {inst_val[31:12], 12'b0};
assign immS = {{20{inst_val[31]}}, inst_val[31:25], inst_val[11:7]};
assign immB = {{20{inst_val[31]}}, inst_val[7], inst_val[30:25], inst_val[11:8], 1'b0};
assign immJ = {{12{inst_val[31]}}, inst_val[19:12], inst_val[20], inst_val[30:21], 1'b0};

always @(*) begin
    case (ext_op)
    3'b000: imm_out = immI;
    3'b001: imm_out = immU;
    3'b010: imm_out = immS;
    3'b011: imm_out = immB;
    3'b100: imm_out = immJ;
    default: imm_out = 32'hxxxx_xxxx;
    endcase
end

endmodule

